1. Field of the Invention
Embodiments of the invention relate generally to a level shifting circuit for a semiconductor device. More particularly, embodiments of the invention relate to a level shifting circuit adapted to reduce the cost and testing time required to produce the semiconductor device.
A claim of priority is made to Korean Patent Application No. 2006-43587, filed May 15, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the degree of integration and performance of modern semiconductor devices such as microprocessors continues to increase, the power level required to operate these devices tends to decrease accordingly. As a result, in some semiconductor devices, different power levels are required for different components. In addition, these semiconductor devices may also include both analog and digital components that make use of the different power levels. Examples of such devices include high speed digital communication systems, high resolution high speed displays, and high capacity data storage systems, to name but a few.
In order to provide the different power levels to the different components, modern semiconductor devices often include level shifting circuit(s) adapted to modify a power supply signal according to the requirements of the different components.
As an example, FIG. 1 illustrates a conventional level shifting circuit for a semiconductor device. The level shifting circuit of FIG. 1 comprises a level shifting portion 10 and a driving portion 20. Level shifting portion 10 comprises a power voltage selecting portion 11 and a level shifter 12, and driving portion 20 comprises first and second driving units 21 and 22.
Power voltage selecting portion 11 receives first and second power voltages V1 and V2, which have different voltage levels. Power voltage selecting portion 11 selects one of power voltages V1 and V2 and outputs the selected power voltage as a level shifter power voltage LS_P.
Level shifter 12 receives level shifter power voltage LS_P and an input signal VIN and modifies the level of input signal VIN according to level shifter power voltage LS_P to produce a level shifter output signal LS_OUT. For example, where level shifter power voltage LS_P is generated as power voltage V1, level shifter 12 modifies input signal VIN according to the level of power voltage V1 to generate level shifter output signal LS_OUT.
Driving portion 20 receives level shifter power voltage LS_P from power voltage selecting portion 11 and level shifter output signal LS_OUT from level shifter 12 and delays and amplifies level shifter output signal LS_OUT under the control of level shifter power voltage LS_P to produce a power voltage output signal VOUT.
To provide different components in the semiconductor device with different operating voltages, power voltage selecting portion 11 controls the level of input signal VIN based on first and second power voltages V1 and V2. However, in order to provide first and second power voltages V1 and V2 to level shifter 12, power voltage selecting portion 11 generally requires a separate metal layer and a separate semiconductor well region for each of the first and second power voltages V1 and V2. Unfortunately, the additional metal layer and semiconductor well region add to the time and cost required to manufacture and test power voltage selecting unit.
The operation of level shifter 12 and driving portion 20 is explained in further detail below with reference to FIGS. 2 and 3, respectively.
FIG. 2 is a circuit diagram illustrating a conventional implementation of level shifter 12. Referring to FIG. 2, the level shifter includes negative metal-oxide semiconductor (NMOS) transistors N1, N2, N3, and N4, positive metal-oxide semiconductor (PMOS) transistors P1 and P2, and an inverter INV.
Level shifter power voltage LS_P is applied to respective upper terminals of PMOS transistors P1 and P2 and the respective gates of NMOS transistors N1 and N3. NMOS transistor N1 is connected between first PMOS transistor P1 and NMOS transistor N2. NMOS transistor N2 is connected between NMOS transistor N1 and ground. NMOS transistor N3 is connected between PMOS transistor P2 and NMOS transistor N4. NMOS transistor N4 is connected between NMOS transistor N3 and ground.
Input signal VIN is applied to the gate of NMOS transistor N2, and the input of inverter INV. Inverter INV inverts input signal VIN to produce an inverted input signal/VIN and applies inverted input signal/VIN to the gate of NMOS transistor N4. The gate of PMOS transistor P1 is connected to a lower terminal of PMOS transistor P2 to form a second output terminal T2 of level shifter 12, and the gate of PMOS transistor P2 is connected to a lower terminal of PMOS transistor P1 to form a first output terminal T1. Output signal LS_OUT is apparent at first output terminal T1.
Level shifter power voltage LS_P is applied to the respective gates of NMOS transistors N1 and N3 to turn on NMOS transistors N1 and N3.
Where input signal VIN has a logic level “low”, NMOS transistor N2 is turned off and NMOS transistor N4 is turned on. As a result, the voltage level of second output terminal T2 is pulled to ground VSS and PMOS transistor P1 is turned on. Accordingly, first output terminal T1 assumes level shifter power voltage LS_P and PMOS transistor P2 is turned off. Since the voltage level of output terminal T1 is level shifter power voltage LS_P, level shifter power voltage LS_P level is output from first output terminal T1 as output signal LS_OUT
On the other hand, where input signal VIN has a logic level “high”, NMOS transistor N2 is turned on, and NMOS transistor N4 is turned off. As a result, the voltage level of first output terminal T1 is pulled to ground VSS and PMOS transistor P2 is turned on. Accordingly, second output terminal T2 assumes level shifter power voltage LS_P and PMOS transistor P1 is turned off. Since first output terminal T1 is pulled to ground VSS, ground VSS is output from first output terminal T1 as output signal LS_OUT.
FIG. 3 is a circuit diagram illustrating one conventional implementation of driving portion 20, including first and second driving units 21 and 22.
Referring to FIG. 3, first driving circuit 21 comprises a PMOS transistor P3 and NMOS transistors N7 and N9 which are serially connected to each other. Level shifter power voltage LS_P is applied to the an upper terminal of PMOS transistor P3 and the gate of NMOS transistor N7. First output terminal T1 of level shifter 12 is connected to the respective gates of PMOS transistor P3 and NMOS transistor N9. An output terminal of first driving circuit 21 is formed at a connection point between NMOS transistor N7 and PMOS transistor P3.
Second driving circuit 22 has a similar configuration to first driving circuit 21. In second driving circuit 22, the output terminal of first driving circuit 21 is connected to the respective gates of a PMOS transistor P4 and a NMOS transistor N10. An output terminal of second driving circuit 22 is formed at a connection point between PMOS transistor P4 and NMOS transistor N10. Power voltage output signal VOUT of level shifting circuit 12 is output through the output terminal of second driving circuit 22.
The basic operation of level shifting circuit 12 is explained below in still further detail with reference to FIGS. 1 through 3.
Power voltage selecting portion 11 selects between first and second power voltages V1 and V2. For explanation purposes, it will be assumed that second power voltage V2 has a higher level than first power voltage V1. Power voltage selection circuit 11 then outputs the selected power voltage as level shifter power voltage LS_P. Level shifter 12 and first and second driving units 21 and 22 operate according to level shifter power voltage LS_P and produce power voltage output signal VOUT.
Where level shifter power voltage LS_P is commonly applied to the respective gates of NMOS transistors N1 and N3 in level shifter 12 and to the respective gates of NMOS transistors N7 and N8 in first and second driving circuits, NMOS transistors N1, N3, N7, and N8 are turned on.
Thus, where input signal VIN has logic level “low”, level shifter power voltage LS_P level is output from first output terminal T1 of level shifter 12, and ground VSS is output from second output terminal T2 of level shifter 12.
The output of first output terminal T1 having level shifter power voltage LS_P is applied to the respective gates of PMOS transistor P3 and NMOS transistor N9 to turn off PMOS transistor P3 and to turn on NMOS transistor N9. As a result, ground VSS is output from the output terminal of first driving circuit 21. The output of first driving circuit 21 is applied to the respective gates of PMOS transistor P4 and NMOS transistor N10 to turn on PMOS transistor P4 and to turn off NMOS transistor N10. As a result, level shifter power voltage LS_P level is output from the output terminal of second driving circuit 22.
Where input signal VIN has logic level “high”, ground VSS is output from first output terminal T1 of level shifter 12 and level shifter power voltage LS_P is output from second output terminal T2 of level shifter 12.
The voltage level of first output terminal T1 is applied to the respective gates of PMOS transistor P3 and NMOS transistor N9 to turn on PMOS transistor P3 turned on and to turn off NMOS transistor N9. As a result, level shifter power voltage LS_P level is output from the output terminal of first driving circuit 21. The output of first driving circuit 21 is applied to the respective gates of PMOS transistor P4 and NMOS transistor N10 to turn off PMOS transistor P4 and to turn on NMOS transistor N10. As a result, ground VSS is output from the output terminal of second driving circuit 22.
As described above, one of the unfortunate drawbacks of the conventional level shifting circuit is that a plurality of metal layers must be formed to provide the power supply signal with multiple different levels. This tends to increase the cost and time required to manufacture and test the level shifting circuit. In addition, once the level shifting circuit is completed, it is not possible to change the number of different levels with which the power supply signal can be supplied because the number of metal layers in the level shifting circuit cannot be dynamically changed.